`default_nettype none

`define CLK_FREQ 27_000_000
`define DIV_CLK_DEFAULT (`CLK_FREQ / 1) // 默认时钟为1hz

module test_dreg_m (
    input rst_w_ni,
    input clk_w_i,
    input key_b_w_ni,

    output led_red_w_no,
    output led_green_w_no
);
    wire arsr_w_nl;
    arsr_m arsr_i_l (
        .rst_w_ni(rst_w_ni),
        .clk_w_i (clk_w_i),

        .rst_w_no(arsr_w_nl)
    );

    wire reg_clk_w_l;

    clk_even_div_m #(
        .DIV_DIV_2_CP_I(`DIV_CLK_DEFAULT / 2)
    ) default_div_i_l (
        .rst_w_ni(arsr_w_nl),
        .clk_w_i (clk_w_i),

        .clk_w_o(reg_clk_w_l)
    );

    dreg_m #(
        .WIDTH_CP_I(1),
        .INIT_VALUE_CP_I(-1)
    ) dreg_i_l (
        .rst_w_ni(arsr_w_nl),
        .clk_w_i(reg_clk_w_l),
        .set_en_w_pi(1),
        .set_wp_i(key_b_w_ni),

        .get_wp_o(led_green_w_no)
    );

    assign led_red_w_no = reg_clk_w_l;
endmodule
